Current Research

The Internet of Things (IoT) has gained significant importance due to its versatile applications in various domains, including smart homes, wearable technology, and industrial automation. However, a common challenge faced by IoT devices is the need for high-speed, short-range communication that is also power-efficient. In this research, our focus is to address this challenge by designing and developing an energy-efficient serial link system specifically tailored for near-sensor applications, with an emphasis on achieving a minimal absolute power consumption.

Contact: Sina Arjmandpour

For wearable and implantable devices, reliable biopotential recording should be ensured even under large artifacts caused by the user’s motion or concurrent electrical stimulation, which can be larger than 100mVPP at the recording IC input. A wide dynamic range (DR) is required for such an artifact-tolerant biopotential-acquisition IC. In addition, ZIN should be large enough to minimize input signal attenuation and common-mode-to-differential-mode conversion of artifacts occurring at the electrode interface. The recording IC should also consume low power for long-time operation with a limited-size battery. In this context, this paper presents an input-impedance-boosted NS-SAR-nested DSM with high DR and power efficiency.

Contact Menghe Jin

Recently, All digital phased locked loops (ADPLL) are becoming popular in wireless communication applications because of their small size, reconfigurability, and scalability. For a better performance in case of their output spectrum, a power-hungry time-to-digital converter (TDC) is required. Besides in multi-bit TDC, calibration is mandatory to alleviate the non-linearity effects on the spectral purity. On the other hand, the Bang-bang phase detector can be used as an alternative for power-hungry TDC in ADPLLs and eliminates TDC nonlinearity issues. Furthermore, Digital-to-time-converters (DTC) enables Fractional-N synthesis in Bang-bang PLLs. However, due to the hard non-linear behavior of the phase detector and DTC non-idealities, Bang-bang PLLs suffers from spurious tones in their spectrum. In this research a new technique is going to be used to purify PLL output spectrum and generate an accurate signal for wireless communication circuits.

Contact Long He

To overcome the limitations of the traditional silicon CIS such as pixel size, dynamic range, sensitivity, and manufacturing cost, we are developing next-generation CIS using special photodetector made of new material with optimized readout circuit
 

Contact Kyuik Cho

Traditionally, the crystal oscillator (XO) drives the phase-locked loop (PLL) reference. This work demonstrates how a PLL-XO co-design with a bidirectional signal flow would improve the performancefor both.

We present a power-efficient and low-jitter frequency generation and synthesis architecture that leverages a phase-locked loop and crystal scillator co-design, integrated with a pulse-injection XO driver. The proposed co-design exploits the low-jitter and fine phase resolution of the PLL output to inject energy into the XO precisely at low-impulse-sensitivity-function points, enhancing XO performance and subsequently reducing the in-band phase noise of the PLL. In addition, a low-kickback reference buffer is introduced, utilizing a cascoded transistor to mitigate buffer-induced switching kickback and further suppress buffer phase noise. Fabricated in a 22-nm FDSOI process, the prototype occupies an active area of 1.14 mm2, with the pulse-injection driver consuming only 0.014 mm2. The measured integrated jitter from 1 kHz to 100 MHz is 54.5 fsrms at 4.6 GHz, while the reference and second harmonic spurs are −71 and −70.4 dBc, respectively. The complete system consumes 7.24 mW, including 1.92 mW for the pulse-injection driver, and achieves a jitter figure-of-merit (FoM) of −256.7 dB, capturing the combined contributions of the PLL, XO, and reference buffer.

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Contact Can Livanelioglu

Neurological disorders in patients have become an increasing burden in societies and the research field attracts more attention. A better  understanding of the brain and neuro system is needed. Since the number
of electrophysiological signals generated by neurons are normally massive, a large scale, high accuracy, intense density and robust artificial device is needed. Through the recording of optical or electrical signals generated by neurons, such as action potentials (APs) and local-field potentials (LFPs), single-neuron behaviour and neural signalling in neuronal networks can be studied.Microelectrode Array (MEA) has been one of the most efficient ways of acquiring neural signals from a large number of neurons in terms of number of recording sites, temporal resolution, spatial resolution, and signal-to-noise ratio. MEAs are devices that contain multiple microelectrodes that can be used to obtain or deliver neural signals and serve as a neural interface that connect neurons to detecting devices. They play an important role in understanding the electrophysiological activity of the nervous system, allowing reading and stimulating multiple cells simultaneously. MEAs can be practical in studying pharmacological effects on dissociated cultures, electrical activity from extracellular networks of cardiac cells, and neurons in organs such as the heart and brain.

In this doctorate, my focus will be on designing a neural interface using a new neural signal detecting scheme with a novel cross coupled MEA that senses the electrical double layer (EDL) capacitance as a function of the ion concentration released by neurons. 

Contact Tianyi Zhang