Past Research
With the unending evolution of wireless communications and unceasing growth of RF system-on-chip (SoC) market, power-efficient frequency synthesis solutions with higher spectral purity, lower power and better robustness are more crucial than ever. Increasingly stringent specifications are imposed on integrated phase noise (IPN) and spur levels to fulfill related requirements, such as transmitter error vector magnitude (EVM), receiver sensitivity, and blocker tolerance. For instance, the ever-growing quests for higher data rates (Fig. (a)) have led to the utilization of dense constellations, such as 256-QAM (5G NR) and even 1024-QAM (802.11ax). Meanwhile, power consumption is another important concern as these handsets operate on batteries. As indicated by Fig. (b), the RF front-end consumes significant power for typical use cases of mobile terminals such as phone calls and web surfing. Furthermore, the frequency synthesis, leveraged as LOs in RF transceivers, consumes significant power compared to the total budget. Therefore, the main goal of the research is to seek an alternative and innovative way of frequency synthesis by phaselocked architecture, that demonstrates better performance at a lower cost with lower power.
Neural signal can be widely used for diagnosing the disease. For measuring the neural signal, the previous work such as medical instruments has difficulty to measure the signal inside of the body due to its bulkiness.
Neural recording IC enables to measure the signal inside of the body thanks to its compactness and low power.
There are interference for the neural recording IC such as current stimulation noise. Interference-robust neural recording IC can measure the neural signal more reliably regardless of the existence of the interference.
In wireline link, energy efficiency is a figure of merit that is given as ratio between total energy consumption and data-rate. It defines how much energy is consumed for communication between transmitter and receiver to send and recognize the bit data respectively.
However, due to ever increasing throughput and complexity in signaling method, competitive number for energy efficiency is challenging.
In this research, transceiver architecture and circuit techniques are proposed to achieve the best energy efficiency in wireline link.
Large portion of energy consumption in wireline transceiver circuit is from clocking, serializer and output driver from transmitter side, DSP engine for equalization and data post processing in receiver side. Also, the requirement of impedance matching between transmitter and receiver consumes significant power. In this research, transceiver architecture and circuit techniques are proposed to relieve the energy consumption in the core blocks of wireline transceiver.
The goal of this research is to propose and verify ultra-low power transceiver that achieves state-of-the-art energy efficiency in the field of wireline link.
VLSI 2018
Neural recording sensor systems require miniaturization to limit brain tissue damage and accommodate tightly spaced electrodes. At the same time, neural potential sensor interface circuits must achieve aggressive input referred noise levels to monitor neural signals with sufficient accuracy. Given the small size and close proximity to sensitive brain tissue, power consumption is also highly constrained to meet strict tissue heating limits. In this work, we propose a new neural recording amplifier that achieves an NEF of 2.2 while meeting aggressive specifications such as > 100MΩ input impedance, > 70dB power supply rejection and common mode rejection ratios. We use a pre-amplifier stage that performs discrete-time parametric amplification based on MOS C-V characteristics. The sampling-induced kT/C noise is minimized by oversampling the input signal. The resulting power overhead is limited with stepwise charging and discharging of the source voltage in the parametric amplifier. Altogether, the design achieves the lowest-reported NEF among neural amplifiers while consuming 5.5uW with 1Hz – 8kHz bandwidth.
ISSCC 2016 JSSC 2018
Digital PLLs are now popular for on-chip clock generation due to their small size and technology portability. Variability tolerance is a key design challenge when designing the PLLs in an advanced CMOS technology. Environmental variations such as mismatch, process, supply voltage, and temperature (PVT) perturb device characteristics and result in a change in the performance, such as DCO gain and noise. This work proposed a nested frequency locked-loop (FLL) architecture whose gain is accurately controlled by a capacitor ratio in order to keep the PLL bandwidth insensitive to variations.The noise of the FLL is programmable independently to the oscillation frequency. A noise detector block, using statistical characteristics of a bang-bang PFD (BBPFD) output, is proposed to efficiently sense DCO noise. The proposed PLL dynamically reconfigures the DCO noise from 2.5 to 15ps and self-adjusts its power from 1.7 to 5 mW according to the noise specification.
ISSCC 2016
Miniaturized computing platforms typically operate under restricted battery capacity due to their size. Due to low duty cycles in many sensing applications, sleep mode power can dominate the total energy budget. Wakeup timers are a key always-on component in such sleep modes and must therefore be designed with aggressive power consumption targets (e.g., <10nW). Also, accurate timing generation is critical for peer-to-peer communication between sensor platforms. Although a 32kHz crystal oscillator can provide low power and accurate long-term stability, the requirement of an off-chip component complicates system integration for small wireless sensor nodes (WSNs).
To address this challenge and achieve a WSN timer with single-digit nW power consumption, we propose a new timer using a duty-cycled resistor scheme to increase resistance without impacting area. By generating the duty cycle using the frequency from the timer itself, an accurate on/off ratio is ensured. In addition, a current-reuse scheme is proposed to save power and also eliminates the need for chopping the bias current. Finally, a self-biasing technique is proposed to ensure stable operation and low power consumption across process-voltage-temperature (PVT) variations. Using these techniques, the timer achieves 13.8ppm/°C (−25 to 85°C) at 3kHz and consumes 4.7nW while showing less than 1.5× power variation across temperature.
