Paper accepted at VLSI 2025
We are very proud to announce that our PhD Student Hesam Omdeh Ghiasi had a paper accepted at this year's VLSI Symposium:
A 33aFrms, 3.4pF Base Capacitance, 192fF Input Range, 500kHz Sampling Frequency, Capacitance-to-Voltage Converter Using a Resonant LC Bridge,
Authors: H. Omdeh Ghiasi, S. Arjmandpour and T. Jang, ETH Zurich, Switzerland
This paper presents a resonant LC bridge technique to enhance the performance of the capacitance-to-voltage converter (CVC) by leveraging its passive gain to improve resolution and power consumption. The proposed CVC achieves 1.56mV/fF gain, 33.1aFrms resolution at 500kHz sampling rate while consuming 2.85μW with 3.4pF base capacitance, equivalent to 3.24fJ/conversion-step Walden FoM and 179.12dB Schreier FoM.